/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2021-2024. All rights reserved.
 * Description: RDMA vroce cmdq command format.
 * Create: 2021-12-30
 */

#ifndef ROCE_VROCE_FORMAT_H
#define ROCE_VROCE_FORMAT_H

#include "roce_npu_cmd_defs.h"
#include "roce_npu_cmd_qp_defs.h"
#include "vroce_context_format.h"
#include "mpu_cmd_base_defs.h"

#define	VROCE_CMDQ_BUF_SIZE 2048U
#define VROCE_CMDQ_BUF_HW_RSVD 8
#define VROCE_CMDQ_MAX_DATA_SIZE    \
        (VROCE_CMDQ_BUF_SIZE - VROCE_CMDQ_BUF_HW_RSVD)

typedef struct tag_vroce_cmd_header {
    union {
        u32 value;

        struct {
            u32 version : 8;
            u32 rsvd : 8;
            u32 cmd_bitmask : 16; // CMD_TYPE_BITMASK_E
        } bs;
    } dw0;

    u32 index; // qpn/cqn/srqn/mpt_index/gid idx

    u32 opt; //

    union {
        u32 value;

        struct {
            u32 cmd_type : 8;
            u32 rsvd : 7;
            u32 seg_ext : 1;
            u32 cmd_len : 16; // verbs cmd total len(include cmd_com),unit:byte
        } bs;
    } dw3;
} vroce_cmd_header_s;

typedef struct tag_vroce_ip_ops_attr {
    vroce_cmd_header_s com;
    u8 key[VROCE_ACL_IP_KEY_LEN];
    u8 value[VROCE_ACL_IP_VALUE_LEN];
} vroce_ip_ops_attr_s;

typedef struct tag_vroce_mig_entry_ops_attr {
    vroce_cmd_header_s com;
    u8 key[VROCE_MIG_ENTRY_KEY_LEN];
    u8 value[VROCE_MIG_ENTRY_VALUE_LEN];
} vroce_mig_entry_ops_attr_s;

typedef struct tag_vroce_cmd_mig_common {
    vroce_cmd_header_s com;
    u32 func_id;
} vroce_cmd_mig_common_s;

typedef struct tag_vroce_cmd_mig_query_num_outbuf {
    union {
        u32 value;
        struct {
#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN))
            u32 rsvd : 8;
            u32 status : 8;
            u32 num : 16;
#else
            u32 num : 16;
            u32 status : 8;
            u32 rsvd : 8;
#endif
        } bs;
    };
} vroce_cmd_mig_query_num_outbuf_s;

typedef struct tag_vroce_cmd_mig_rollback_status_outbuf {
    union {
        u32 value;
        struct {
#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN))
            u32 rollback_status : 1;
            u32 rsvd : 31;
#else
            u32 rsvd : 31;
            u32 rollback_status : 1;
#endif
        } bs;
    };
} vroce_cmd_mig_rollback_status_outbuf_s;

typedef struct tag_vroce_cmd_mig_dirty_drain {
    vroce_cmd_header_s com;
    u32 func_id;
    u32 queue_idx;
} vroce_cmd_mig_dirty_drain_s;

typedef struct tag_vroce_cmd_mig_restore {
    vroce_cmd_header_s com;
    u32 func_id;
    u32 loop_idx;
    u32 loop_max;
    u32 xid_start;
    u32 xid_end;
} vroce_cmd_mig_restore_s;

typedef struct tag_vroce_cmd_mig_cache_out {
    vroce_cmd_mig_common_s mig_com;
    vroce_mig_cache_line_s cache_line[VROCE_MIG_CACHE_LINE_NUM];
} vroce_cmd_mig_cache_out_s;

typedef struct tag_vroce_cmd_mig_cache_out_outbuf {
    u32 status;
} vroce_cmd_mig_cache_out_outbuf_s;

typedef struct tag_vroce_cmd_mig_qurey_gid {
    vroce_cmd_header_s com;
    u16 func_id;
    u16 rsvd;
} vroce_cmd_mig_qurey_gid_s;

typedef struct tag_vorce_cmd_mig_query_gid_outbuf {
    roce_gid_entry_s gid_entry;
} vorce_cmd_mig_query_gid_outbuf_s;

typedef struct tag_vroce_cmd_mig_update_gid {
    vroce_cmd_header_s com;
    u16 func_id;
    u16 rsvd;
    roce_gid_entry_s gid_entry;
} vroce_cmd_mig_update_gid_s;

#endif /* ROCE_VROCE_FORMAT_H */